1. Field of the Invention
This invention relates generally to the field of computer design and, more particularly, to the design of a protocol for transitioning one or more sections of a processing unit in and out of a zero-power state.
2. Description of the Related Art
The ever increasing advances in silicon process technology and reduction of transistor geometry makes static power (leakage) a more significant contributor in the power budget of processors (CPUs). Currently known CPU ACPI (Advanced Configuration and Power Interface) and ACPI-based low-power states (C1-C5) are very instrumental in eliminating dynamic power consumption and reducing the CPU static power. The ACPI is an open industry standard originally developed by Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba, and defines common interfaces for hardware recognition, motherboard and device configuration and power management. The most widely recognized element of ACPI is power management, offering improvements over past power management methods by giving the Operating System (OS) control of power management, in contrast with prior power management models where power management control was mainly under the control of the BIOS, with limited intervention from the OS. In ACPI, the BIOS provides the OS with methods for directly controlling the low-level details of the hardware, providing the OS with nearly complete control over the power savings.
Another important feature of ACPI is bringing power management features previously only available in portable computers to desktop computers and servers. For example, systems may be put into extremely low consumption states, i.e., states in which only memory, or not even memory, is powered, but from which “general-purpose events” (GPEs, similar to interrupts, which can be sent by devices such as the real-time clock, keyboard, modem, etc.) can quickly wake the system. ACPI uses its own ACPI Machine Language (or AML) for implementing power event handlers, rather than the native assembly language of the host system, and while the AML code is typically part of firmware (BIOS) it is interpreted by the OS.
The ACPI specifies various groups of states, among them global states, device states, performance states, and processor states. For example, the ACPI standard defines four processor power states, C0-C3. C0 is the operating state. C1 (often referred to as Halt state) is a state in which the processor is not executing instructions, but can (essentially) instantaneously return to an executing state. Some processors also support an Enhanced C1 state (CIE) for lower power consumption. C2 (often known as Stop-Clock state) is a state in which the processor maintains all software-visible states at the expense of possibly taking longer to wake up. C3 (often known as Sleep state) is a state in which the processor does not need to keep its cache coherent, but does maintain other states. Some processors have variations on the C3 state (Deep Sleep, Deeper Sleep, etc.) that differ in how long it takes the processor to wake up. While the ACPI specifies 4 states (C0-C3), processors can have independently defined hardware states that range from C0 to C5 and beyond, as previously mentioned. A processor generally supports each of those C-states, which are typically mapped to a particular ACPI C-state depending on the behavior of the processor while in that state, as defined by ACPI. However, none of these states completely eliminates the static power component consumed by the processor. Therefore the efficiency of C1-C5 states for power saving is becoming more limited for advanced CPU manufacturing process technologies and smaller transistor geometries.
Various methods have been proposed and implemented to lower power consumption as much as possible. For example, power consumption may be lowered by sizing-down, invalidating, and eventually turning-off the L2 cache by lowering the retention voltage to a level lower than is needed to retain L2 contents. This is also known as the C5-state. While this offers one possible solution in eliminating the massive L2 component from the static power consumption budget, it does not eliminate the power consumption contribution of smaller arrays (e.g. L1 cache) or regular logic, thus maintaining static power at fairly high level for advanced (45 nm and lower) processes.
A new state, the C6 state, first introduced by Intel in 2007, allows for complete elimination of both dynamic and static components of power consumption, by transitioning the CPU to the zero-state where 0V is applied to the CPU voltage plane, and the CPU clock is completely turned off. It should be noted that the C6-state is not equivalent to system sleep state S3 where most of the system is powered down, and restoration to the C0-state requires an extended period of time, oftentimes in the range of many seconds. The C6-state can be applied to a single-core processor or to any core or group of cores in multi-core processors, while keeping other cores and system components (chipset, I/O, DRAM) in fully functional state. At the moment the OS indicates the need for allocating some task/process on a given CPU that is presently in the C6-state, that given CPU is powered-up and becomes available for executing the requested task/process. Generally, the C6-state provides enablement for a more aggressive performance-oriented approach to CPU process technology (for example reducing the transistor effective length), which would otherwise be impeded by the inevitable increase in static power consumption. Effectively managing a processor's transitioning in and out of the C6-state can therefore lead to improved power management and result in reduced overall power consumption.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.